Microelectronics & VLSI · IIT Roorkee

Rahul K Mahato.

M.Tech · Microelectronics & VLSI

I work across digital design, VLSI circuits, memory technologies and compute-in-memory architectures, with a focus on designing and simulating efficient hardware systems.

Explore my work ↗Download CV
Open to research, collaboration & technical conversations
Rahul K Mahato
Electronics & Communication EngineerM.Tech · Microelectronics & VLSI · IIT Roorkee
DIGITAL DESIGN / VLSI / FEFET / CIM
01 — A little about me

Building at the intersection of circuits & computing.

RAHUL / 2026

I’m Rahul K Mahato, an Electronics & Communication Engineer and M.Tech candidate in Microelectronics & VLSI at IIT Roorkee.

My work sits at the intersection of digital design, transistor-level circuits, memory-centric computing and emerging non-volatile devices. I enjoy taking an architecture from a logic idea to a transistor-level implementation and simulation.

My current research focuses on FeFET-based compute-in-memory (CIM), including an 8×8 analog CIM array for 8-bit MAC operations, alongside SRAM-based Boolean in-memory computing.

EducationM.Tech, Microelectronics & VLSI — IIT Roorkee
UndergraduateB.Tech, Electronics & Communication — MNNIT
FocusVLSI · CIM · FeFET · Low-Power Circuits
Currently exploring

Hardware that brings memory and computation closer together.

FeFETCompute-in-MemoryRTLCMOSSRAMLow Power
02 — Selected work

Projects.

01

Low-Power Supply Dynamic Comparator

Modified double-tail dynamic comparator for ADC applications, designed and simulated at MNNIT.

Cadence Virtuoso90 nmCMOSLow Power
2.70 µWPower0.108 pJEnergy
02

Active RC Filters with Independent Parameter Tuning

Active filter study covering low-pass, high-pass and band-pass configurations with independent parameter tuning in LTspice.

LTspiceAnalog CircuitsLPFHPFBPF
2023Project
03 — Featured research

My M.Tech thesis.

IIT ROORKEE · 2026
FeFET-based Compute-in-Memory

8-bit MAC operations inside an 8×8 analog CIM array.

Design and Simulation of FeFET-Based 8-Bit CIM Array MAC Operations, supervised by Prof. Sudeb Dasgupta & Dr. Sourajeet Roy.

Open PDF
8.59TOPS/W
2.13GOPS
98 µWAverage power
16 nsLatency / cycle

The work investigates Compute-in-Memory as an alternative to data movement in conventional von Neumann systems. The core design is an 8×8 FeFET-based analog CIM array for 8-bit MAC operations, using a GlobalFoundries 28 nm HKMG process, Si:HfO₂ ferroelectric gate stack, PWM input encoding across four cycles and a hierarchical 1C-2C-4C capacitive shift-and-add network.

Additional work includes a Dual-Port 8T SRAM-based Boolean in-memory computing cell performing NAND, NOR, XOR and XNOR directly on SRAM bitlines. The designs are simulated in Cadence Virtuoso using BSIM + Verilog-A compact modeling.

04 — What I work with

Skills & tools.

Digital Design

Verilog
RTL Design
Digital Logic

VLSI & Circuits

Cadence Virtuoso
CMOS
SRAM
FeFET

Simulation

Spectre
LTspice
Xilinx / Vivado

Research

Compute-in-Memory
Analog CIM
Memory Circuits
Low Power

05 — How I approach a design

From idea to simulation.

01SPECIFYProblem definition
02ARCHITECTCell / system design
03IMPLEMENTRTL / transistor level
04SIMULATECadence / SPICE
05OPTIMIZEPower · speed · area
06 — Education

Academic journey.

2024 — 2026

M.Tech · Microelectronics & VLSI

IIT Roorkee · Department of Electronics & Communication Engineering

B.Tech

Electronics & Communication Engineering

MNNIT · Project work in low-power VLSI and active analog filters

07 — Notes & thoughts

Writing.

08 — Get in touch

Let's connect.

Interested in research, collaboration, or technology? Let’s connect.